1. Field
Exemplary embodiments of the present invention relate to an image sensor and, more particularly, to a double data rate (DDR) counter for supporting digital double sampling (DDS), an analog-to-digital converting apparatus and a complementary metal oxide semiconductor (CMOS) image sensor including the same.
Digital double sampling is excellent at removing offset in single slope analog-to-digital converters (ADC). In the embodiments of the present invention, a single slope ADC will be used as an example. However, the present invention may be applied in various mechanisms, including double data rate counters.
2. Description of the Related Art
Counters are used in various electronic devices for converting physical quantities, such as light intensity, sound intensity, or time into a digital signal.
Image sensors absorb incident light on a pixel array and create an analog signal. The analog signal then needs to be transformed into a digital signal for data transfer, processing, and storage. This requires the use of an analog-to-digital converter (ADC). The ADC may be implemented with a counter that performs a counting operation using a dock.
The operating speed and power consumption of the counter has a direct influence on the performance of the system or device in which it is incorporated. In particular, CMOS image sensors often include a plurality of counters to convert analog signals, outputted from an active pixel sensor array column by column, into digital signals. The number of counters may be increased to increase the resolution of the CMOS image sensor. As the number of counters increases, the operation speed and power consumption of the counters become an important factor in determining overall performance of the image sensor.
With the increase in resolution and frame rate of CMOS images sensors, the amount of data to be processed within the CMOS image sensor has increased. Most common CMOS image sensors use a single slope ADC to, convert analog voltages from pixels into digital values. In particular a single slope ADC based on column parallel readout architecture significantly reduces the analog-to-digital conversion rate, has low power consumption, and occupies a small area.
The single slope analog-digital conversion time is determined by 1/fclk*2N where N represents analog-digital conversion resolution and fclk represents the frequency of the single slope ADC. Thus, with an increase in resolution and frame rate of the CMOS image sensor, the frequency fclk of the single slope ADC needs to be increased as well. However, increases in the frequency may increase the parasitic RC (RC delay) of the clock signal and thus increase power consumption. Furthermore, the physical limits of the RC time constant make it difficult to operate at a high clock speed.
Thus, DDR counting techniques have been proposed to reduce the clock speed of single slope ADCs, DDR counting techniques include a first DDR counting method using a logic level of a sampled clock as the least significant bit (LSB) data and a second DDR counting method using an XOR circuit. As the DDR counter and the first DDR counting method use a clock as the LSB data, the DDR counter has lower power consumption than the DDR counter using an XOR circuit based on the second DDR counting method because the logic gates are required to toggle less often.
However, the above-described DDR counting techniques have a disadvantage in that a bit-wise inversion (BWI) counter or up-down counter is required. Furthermore, each of the counters has a structure in which a logic gate is provided between T flip-flops included in the counter. In this case, the area of the counter is increased and a logic gate is additionally used in the counting signal path and thus increases power consumption.
Conventional DDR counters, in which a rising edge appears first, may be applied to BWI technology for performing digital double sampling (DDS).
The conventional DDR counter may not be applied to the DDS counting methods using only up-counting or down-counting. This is because one of two counting operations is first performed at a falling edge of the clock signal at all times. Further ore, the BWI method includes a multiplexer used for each cell and a D flip-flop used for a control block. Thus, the area of the counter is inevitably increased.
On the other hand, conventional single-direction counting techniques do not require a logic gate between T flip-flops and have a simple structure. However, there are currently no DDR counters suitable for single-direction counting techniques.